As the development of the semiconductor process, the thickness of gate-oxide is becoming thinner such that the electronic device is more adapted to the high frequency and high speed environment. The same time that the core power supply voltage (VDD) is also decreasing, however, the board voltage (VCC) is still remaining at between 3.3V to 5V, such as PCI-X interface. Hence, the high-voltage stress across the gate oxide becomes a serious problem in deep submicron (DSM) processes. To avoid using a high-cost tailor-make integrated circuit (IC) to solve the aforementioned problem, a circuit capable of receiving a high-voltage input signal, but being consisted by only using low-voltage devices with thin gate oxide is required such that the cost thereof can be decreased, and the IC volume is reduced for improving the easiness of designing PCB layout.
Recently, the number of transistors per IC grows due to higher computing demand, shrinking linewidth, and growth of die size. Even if die size were a constant, the number of transistors per IC would grow so that the Metal-Oxide Semiconductor Field Effect Transistors (MOSFET) is heavily used in current IC design. In constant electrical field scaling, not only the dimensions of MOSFET are shrunk, but also the voltages of the MOSFET are scaled. Consequently, semiconductor chips with different power supply voltage may exist in a same computer system or sub-system. In this regard, the I/O interfaces arranged between the foregoing chips should be capable of preventing the high voltage overstress and illegal current leakage path. The output buffer of the present invention is the answer for the above problems.
Refer to FIG. 1, which is a circuitry of a conventional tri-state output buffer. The tri-state output buffer used a NAND gate and a NOR gate as input end elements where the three signal input ends are the following: the signal input end EN of the NAND gate, the signal input end ENB of the NOR gate, and the signal input end IN formed by connecting a leg of the NADN gate and a leg of the NOR gate. In addition, the output end of the NAND gate is connected to the p-channel metal oxide semiconductor (PMOS) P1 through a level converter, and the output end of the NOR gate is connected directly to a n-channel metal oxide semiconductor (NMOS) N1. Since both the VDDs of the P1 and N1 are 2.5V that compare to the VCC, which is 3.3V or 5V, the transistors are prone to burn out. Hence, a new buffer architecture capable of receiving a high-voltage that can avoid the need to use other expensive tailor-make transistors in the circuitry thereof is required.
Please refer to FIG. 2, which shows a conventional level converter. The level converter of FIG. 2 is consisted of six transistors, which are P1, P2, P3, N1, N2, and N3. Wherein, the transistors P1, P2, N1, and N2 are the I/O (high-voltage (VDDQ)) devices and the transistors P3 and N3 are the core (low-voltage (VDD)) devices. Assume that VDD is at 1V and VCC is at 3.3V. The voltage gap between VCC and VDD is so large that the level converter can not operate correctly. Besides, the devices will have high-voltage gate-oxide stress. Thus, a new level converter is also required and presented in the present invention.